When the manufacturing technology moves to deep sub-micron process, physical defects such as shorts, opens, and bridges introduced during fabrication process show up not only at interconnects between CMOS (Complementary Metal-Oxide Semiconductor) cell terminals, but also inside the CMOS cells. The physical failure analysis had revealed that open defects are one of major failure mechanisms during manufacture. Open defects (sometimes referred to as opens) can be classified into two categories: interconnect opens and cell internal opens. The interconnect open is a defect located at a net connecting cell terminals. A complete interconnect open makes the cell input float and the voltage at the floating net is hard to predict. A resistive interconnect open (interconnect open with finite resistance) introduces extra delay to the circuit and may make the chip fail to operate at the functional speed. The cell internal open is a defect located inside the CMOS cells and this type of defects includes transistor opens, transistor terminal opens, net opens, and open vias, etc. FIG. 3 shows an example of various open defects inside and outside of a CMOS cell. In the figure, a transistor open 330, a transistor terminal open 340, and a net open 320 are inside a CMOS cell 300 while an interconnect open 310 are outside the CMOS cell 300.
The behavior of complete interconnect opens had been studied extensively in the past. The voltage at an open net may be determined by parasitic capacitances between the open net and its neighboring nets, transistor capacitances to the open net, trapped charge deposited on the open net, and RC interconnect behavior of the die surface. The resistive interconnect open is often targeted as a delay fault. To detect the defect, it needs to apply a transition test including two vectors that launch the transition at the fault site and propagate the fault effect to an observation point such as a scan cell or a primary output.
Inside a CMOS cell, a transistor open or a transistor terminal open causes the transistor non-conducting permanently. The defect blocks the charging/discharging path(s) to/from internal nodes. This type of open defects is modeled as transistor stuck-open (TSOP) fault. To detect an n-FET (p-FET) (field-effect transistor) TSOP fault, a test includes two vectors. The first vector turns on one or more charging (discharging) paths that drive the output of the CMOS cell to 1(0) and subsequently the second vector turns on the discharging (charging) path passing through the transistor. A transistor open or a transistor terminal open associated with the transistor can be detected as it breaks the discharging (charging) path and the output of the CMOS cell holds its previous value 1(0) rather than 0(1).
FIG. 4 illustrates an example of a NAND cell (410) and an example of a NOR cell (420). When the first vector applied to cell inputs A and B of the NAND cell 410 is (1,1), cell output Z will be driven to 0 through transistors N1 and N2. When the second vector (0,1) is then applied, the cell output Z is charged to 1 through transistor P1 (a p-FET transistor) assuming there is no defect on the charging path. If there is an open defect associated with the transistor P1, the cell output Z of the NAND cell 410 will stay at 0 instead due to the open on the charging path.
To detect an open defect associated with N1, an n-FET transistor of the same cell, the first vector applied to the cell inputs A and B can be (0,0) or (0,1) which is denoted as (0,X)) and the second vector needs to be (1,1). The cell output Z of the NAND cell 410 is first charged to 1 through the transistor P1 or either of the transistors P1 and P2. The discharging path through N1 and N2 is activated by the second vector and the cell output Z is driven to “0”. However, if there is an open defect associated with N1, the discharging path will be blocked and the cell output Z of the NAND cell 410 will remain at “1”.
Similarly, the input assignment for detecting an open defect associated with P1 in the NOR cell 420 is (1,X) for the first vector and (0,0) for the second vector. To detect an open defect associated with N1 in the same cell, the input assignment is (0,0) for the first vector and (1,0) for the second vector. FIG. 5 summarizes the tests (input assignments and good machine output values) for detecting transistor stuck-open faults inside three primitive cells implementing the logic functions of the primitive gates NOT, NAND, and NOR. In the figure, the left column and the right column of the input assignment and the output for each of the gates represent values for the first clock cycle and the second clock cycle, respectively.
The transistor stuck-open fault belongs to a sequence-dependent failure rather than a timing failure. This is in contrast to the conventional transition fault which represents a gross delay at a cell terminal. The transition fault assumes that the delay at the fault site is large enough to cause logic failure. To detect a slow-to-rise (slow-to-fall) fault, the test also includes two vectors but is applied at the functional speed. The first vector sets up an initial value 0(1) at the fault site. The second vector switches the fault site value to 1(0) and propagates the activated stuck-at-0(1) fault at the fault site to an observation point. FIG. 6 shows the necessary assignments to detect slow-to-rise and slow-to-fall transition faults at the input A of the three primitive cells shown in FIG. 5. Comparing FIGS. 5 and 6, it is evident that the necessary input assignments for detecting transistor stuck-open faults are more stringent than those for detecting transition faults. A test pattern generated for detecting a transistor stuck-open fault inside a primitive cell can also detect a transition fault at the gate terminal of the primitive cell. It is unnecessary the case the other way around, however.
The above-mentioned method for detecting transistor stuck-open faults inside primitive cells, however, cannot be applied directly to complex cells. A primitive cell or a primitive logic gate is one where all the inputs directly drive a gate of a transistor in a switch-network that is connected to the output. In CMOS, common primitive gates include NOT, NAND, and NOR gates. Sometimes, an AND/OR gates, which can be assembled using a NAND/NOR gate and a NOT gate, may be treated as a primitive gate and be used in a gate-level netlist. A complex cell implements a non-primitive Boolean function and can be represented with two or more primitive logic gates. The representation is often not unique.
FIG. 7 illustrates two gate-level models, 710 and 720, for a complex cell 700. The complex cell 700 implements the logic function of A(B+C). To generate the test for a stuck-open fault in the complex cell 700, the method proposed in N. Devtaprasanna, et al., “A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults,” in European Test Symp., pp. 185-192, 2006 (referred to as the Devtaprasanna method), which is incorporated herein by reference, is employed. The test derived for detecting for a stuck-open fault associated with the p-FET P2 transistor using the gate-level model 710 is shown in FIG. 7. This result, however, has a problem because the assignment for input A in the first vector is a don't care bit (“x”). If this don't care bit is filled with “0”, the output Z is driven to “1” by the first vector through the transistor P1 and will stay at “1” after the second vector is applied no matter whether the stuck-open fault associated with the p-FET P2 transistor exists or not.
While the correct result can be obtained when applying the Devtaprasanna method to the gate-level model 720 for detecting a stuck-open fault associated with the p-FET P2 transistor, this gate-level model can lead to a problem for detecting a stuck-open fault associated with the n-FET N2 transistor. FIG. 7 shows the result for the Devtaprasanna method with the assignment in the first vector being don't cares for both inputs A and C. The analysis of the cell 700 shows, however, that they cannot be “1” simultaneous in the first vector because the output Z is driven to “0” though the transistors N1 and N3 by the first vector and will stay at “0” after the second vector is applied no matter whether the stuck-open fault associated with the n-FET N2 transistor exists or not.
The above discussion shows that applying traditional methods to gate-level netlists has drawbacks in detecting transistor stuck-open faults inside complex cells since a complex cell may be represented by more than one functionally equivalent gate-level netlist. While the switch-level netlist (modeling each transistor as being “open,” “close,” and “unkown” and each node (wire) as being 0, 1, and X) of a complex cell can be used to solve the problem, this approach increases the test generation complexity dramatically. Almost all existing ATPG (Automatic Test Pattern Generation) tools generate the tests based on gate-level netlists by modeling the CMOS cells with their functionally equivalent gate level netlists and the fault sites at the cell boundary are targeted during test generation. It is thus desirable to develop a method for detecting transistor stuck-open faults inside complex cells based on gate-level netlists.